1. Field of the Invention
The present invention is directed to integrated circuits and, more particularly, to arrays of devices that are field or mask programmable.
2. Description of the Background
Field programmable gate arrays (FPGA), as the name implies, are user programmable after the manufacturing process is completed. An FPGA typically includes a two dimensional array of configurable logic blocks (CLBs) distributed over the chip. Each of these CLBs includes a block of configurable logic elements (CLEs) and corresponding programmable routing resources. The routing resources associated with the various CLBs can be programmed by the user to provide various connections among the CLEs. In addition, the user can program the CLEs to implement different functions.
The flexibility provided by FPGAs comes at the cost of logic density. For example, suppose that certain CLBs are configured to implement an adder function having a certain number of bits. The CLBs required to implement such an adder function will have a larger layout area than a dedicated adder function having the same number of bits. Thus, FPGAs exhibit a reduced logic density with respect to dedicated circuits because of the additional resources required to provide the routing resources needed so that the CLEs can be user programmable.
It has been recognized that a user programmable interconnect technique or manufacturer programmability just prior to shipment would allow lower tooling costs and faster delivery times. To such an end, gate arrays were developed as an alternative to FPGAs. Non-field programmable gate arrays can be programmed to implement application specific functions. The function of a non-field programmable gate array is defined during the later stages of manufacture, after a defined pattern of transistors has been formed. An example of a non-field programmable gate array is a sea-of-gates (SOG) gate array, which is a mask programmed gate array.
An SOG gate array, in which a pattern of transistors are interconnected by custom patterns of metal lines, has a significantly higher logic density than an FPGA. In an SOG gate array, a predefined pattern of transistors is connected directly with user-defined metal, both to form gates and to interconnect those gates. Consequently, the extensive programmable routing resources required for an FPGA are not present in an SOG gate array. However, non-field programmable gate arrays, such as SOG gate arrays, are inflexible in that they do not provide for field programmability.
It has been recognized that an application specific logic area ASLA may be an equivalent of an FPGA. See, for example, U.S. Pat. No. 5,825,202, U.S. Pat. No. 5,068,603, and U.S. Pat. No. 5,550,893. While those patents recognize the relationship between an ASLA and a FPGA, they do not provide an easily implemented mechanism for producing an ASLA from a FPGA that has been programmed to implement a specific function. Therefore, the need exists for a method and apparatus to easily translate a programmed FPGA to an equivalent ASLA.
The present invention is directed to a xe2x80x9cvia-programmablexe2x80x9d gate array (VPGA). A via is a cut manufactured between two metal layers on an integrated circuit to electrically interconnect two segments of metal on those different layers. A VPGA differs from an FPGA in that the programmability in a VPGA is provided by modification of placement of vias rather than data bits stored in a memory. In the interconnect structure of a VPGA, the programmable interconnect point is a single via, which replaces four to eight transistors in an FPGA. The vias may be used to interconnect logic functions or to implement logic functions.
Another aspect of the present invention allows for the construction of a VPGA whose architecture mimics the architecture of an existing FPGA, with some or all of the field programmability replaced by via-programmability. The proposed architecture of the VPGA is designed such that the corresponding FPGA can be used for design prototyping and the VPGA can use the same bit stream to produce a more robust, higher performance, lower cost integrated circuit or system. The FPGA bitstream is converted to a set of via masks for manufacturing the VPGA.
Another aspect of the present invention is the use of via programmable switch boxes that allow one layer of metal to be connected to another layer of metal through the use of vias without creating dangling wires or adding unnecessary capacitance to the lines. Those, and other advantages and benefits will become apparent from the Description of the Preferred Embodiments herein below.